1 document # sram104 rev c revised november 2007 description the p4c148 and p4c149 are 4,096-bit ultra high-speed static rams organized as 1k x 4. both devices have common input/output ports. the p4c148 enters the standby mode when the chip enable ( ce ) goes high; with cmos input levels, power consumption is extremely low in this mode. the p4c149 features a fast chip select capability using cs . the cmos memories require no clocks or refreshing, and have equal access and cycle times. inputs are fully ttl-compatible. the rams operate from a single 5v 10% tolerance power supply. p4c148, p4c149 ultra high speed 1k x 4 static cmos rams features full cmos, 6t cell high speed (equal access and cycle times) ? 10/12/15/20/25/35/45/55 ns (commercial) ? 15/20/25/35/45/55 ns low power operation single 5v 10% power supply two options ? p4c148 low power standby mode ? p4c149 fast chip select control common input/output ports three-state outputs fully ttl compatible inputs and outputs standard pinout (jedec approved) ? 18 pin 300 mil dip ? 18 pin lcc (295 x 335 mil) [p4c148 only] ? 18 pin lcc (290 x 430 mil) functional block diagram pin configuration access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. cmos is used to reduce power consumption when active; for the p4c148, consumption is further reduced in the standby mode. the p4c148 and p4c149 are available in 18-pin 300 mil dip packages, as well as 2 different lcc packages, providing excellent board level densities. p4c148 dip (c9, d1, p1) p4c149 dip (p1) p4c148 lcc (l7, l7-1) p4c149 lcc (l7)
p4c148/p4c149 page 2 of 10 document # sram104 rev c maximum ratings (1) symbol parameter value unit v cc power supply pin with ? 0.5 to +7 v respect to gnd terminal voltage with ? 0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ? 55 to +125 c temperature range v cc = max., ce , cs = v ih , v out = gnd to v cc symbol parameter value unit t bias temperature under ? 55 to +125 c bias t stg storage temperature ? 65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma capacitances (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) grade (2) commercial military symbol parameter conditions typ. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 7 pf ambient temp 0c to 70c -55c to +125c gnd 0v 0v v cc 5.0v 10% 5.0v 10% recommended operating conditions v oh v ol v ih v il i li i lo i sb i sb1 parameter output high voltage (ttl load) output low voltage (ttl load) input high voltage input low voltage input leakage current output leakage current standby power supply current (ttl input levels) standby power supply current (cmos input levels) test conditions i oh = ?4 ma, v cc = min. v cc = max., v in = gnd to v cc unit v v v ma ma a a v i ol = +8 ma, v cc = min ce v ih , v cc = max., f=max., outputs open ce v hc , v cc = max., f= 0, outputs open v in 0.2v or v in v cc ?0.2v dc electrical characteristics over recommended operating temperature and supply voltage (2) max. 0.4 0.8 sym. min. 2.4 max. 0.4 v cc +0.5 2.2 ?0.5 (3) 0.8 p4c148 p4c149 min. 2.4 2.2 v cc +0.5 ?0.5 (3) mil. comm?l mil. comm?l mil. comm?l mil. comm?l ?10 ?5 ?10 ?5 +10 +5 +10 +5 15 10 30 23 n/a n/a n/a n/a n/a = not applicable parameter commercial symbol unit -35 -25 -20 -15 -12 130 130 120 115 100 100 ma -10 dynamic operating current i cc power dissipation characteristics vs. speed ?10 ?5 +10 +5 +10 +5 ?10 ?5 military -45 95 -55 95 n/a n/a 145 135 125 120 ma 115 115
p4c148/p4c149 page 3 of 10 document # sram104 rev c notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating condi- tions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and timing waveform of read cycle no. 2 (6) timing waveform of read cycle ac characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. ce is low and we is high for read cycle. 6. we is high, and address must be valid prior to or coincident with ce transition low. 7. transition is measured 200mv from steady state voltage prior to change with specified loading in figure 1. this parameter is sampled and not 100% tested. 8. read cycle time is measured from the last valid address to the first transitioning address. min max min max min max min max min max min max min max min max t rc read cycle time 10 12 15 20 25 35 45 55 t aa address access time 10 12 15 20 25 35 45 55 t ac chip enable access time (p4c148) 10 12 15 20 25 35 45 55 t ac chip enable access time (p4c149) 8 10 12 14 15 20 20 25 t oh output hold from address change 33333333 t lz chip enable to output in low z (p4c149) 22222222 t hz chip disable to output in high z (p4c149) 456810141820 t rcs read command setup time 00000000 t rch read command hold time 00000000 t pu chip enable to power up time (p4c148) 00000000 t pd chip disable to power down time (p4c148) 10 12 15 20 25 35 45 55 -45 -55 -15 -20 -25 -35 sym parameter -10 -12
p4c148/p4c149 page 4 of 10 document # sram104 rev c timing waveform of write cycle no. 1 ( we we we we we controlled) (9) notes: 9. ce and we must be low for write cycle. 10. if ce goes high simultaneously with we high, the output remains in a high impedance state. 11. write cycle time is measured from the last valid address to the first transition address. timing waveform of write cycle no. 2 ( ce ce ce ce ce / cs cs cs cs cs controlled) (9) ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) min max min max min max min max min max min max min max min max t wc write cycle time 10 12 15 20 25 35 45 55 t cw chip enable time to end of write 8 10 12 16 20 25 30 35 t aw address valid to end of write 8 10 12 16 20 25 30 35 t as address set-up time 00000000 t wp write pulse width 8 10 12 16 20 25 30 35 t ah address hold time from end of write00000000 t dw data valid to end of write 567912162025 t dh data hold time 00000000 t wz write enable to output in high z 56778121520 t ow output active from end of write 00000000 sym parameter -10 -12 -45 -55 -15 -20 -25 -35
p4c148/p4c149 page 5 of 10 document # sram104 rev c input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce ce ce ce ce we we we we we output power standby h x high z standby read l h d out active write l l high z active ac test conditions truth table figure 1. output load figure 2. thevenin equivalent * including scope and test fixture. note: due to the ultra-high speed of the p4c148/149, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.73v (thevenin voltage) at the comparator input, and a 116 resistor must be used in series with d out to match 166 (thevenin resistance).
p4c148/p4c149 page 6 of 10 document # sram104 rev c selection guide the p4c148/p4c149 are available in the following temperature, speed and package options. * military temperature range with mil-std-883, class b processing. n/a = not available ordering information 10 12 15 20 25 35 45 55 plastic dip -10pc -12pc -15pc -20pc -25pc -35pc -45pc -55pc side brazed dip -10cc -12cc -15cc -20cc -25cc -35cc -45cc -55cc cerdip n/a n/a -15dm -20dm -25dm -35dm -45dm -55dm side brazed dip n/a n/a -15cm -20cm -25cm -35cm -45cm -55cm lcc (290 x 430 mil) n/a n/a -15lm -20lm -25lm -35lm -45lm -55lm lcc (295 x 335 mil) n/a n/a -15lsm -20lsm -25lsm -35lsm -45lsm -55lsm cerdip n/a n/a -15dmb -20dmb -25dmb -35dmb -45dmb -55dmb side brazed dip n/a n/a -15cmb -20cmb -25cmb -35cmb -45cmb -55cmb lcc (290 x 430 mil) n/a n/a -15lmb -20lmb -25lmb -35lmb -45lmb -55lmb lcc (295 x 335 mil) n/a n/a -15lsmb -20lsmb -25lsmb -35lsmb -45lsmb -55lsmb speed (ns) military temperature military processed* temperature range package commercial temperature
p4c148/p4c149 page 7 of 10 document # sram104 rev c pkg # # pins symbol min max a - 0.200 b 0.014 0.026 b2 0.030 0.065 c 0.008 0.018 d - 0.960 e 0.220 0.320 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - 0.100 bsc c9 18 (300 mil) 0.300 bsc pkg # # pins symbol min max a - 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 0.960 e 0.220 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - 0 15 0.100 bsc d1 18 (300 mil) 0.300 bsc side brazed dual in-line packages cerdip dual in-line packages
p4c148/p4c149 page 8 of 10 document # sram104 rev c pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.280 0.305 d1 d2 d3 - 0.305 e 0.417 0.440 e1 e2 e3 - 0.440 e h j l 0.045 0.055 l1 0.075 0.090 l2 0.075 0.148 nd ne 0.020 ref 4 5 0.200 bsc 0.100 bsc 0.050 bsc 0.040 ref l7 18 .150 bsc .075 bsc pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.280 0.305 d1 d2 d3 - 0.305 e 0.345 0.365 e1 e2 e3 - 0.365 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.125 nd ne l7-1 18 .150 bsc .075 bsc 0.020 ref 4 5 0.200 bsc 0.100 bsc 0.050 bsc 0.040 ref rectangular leadless chip carrier rectangular leadless chip carrier (small)
p4c148/p4c149 page 9 of 10 document # sram104 rev c pkg # # pins symbol min max a - 0.210 a1 0.015 - b 0.014 0.022 b2 0.045 0.070 c 0.008 0.014 d 0.880 0.920 e1 0.240 0.280 e 0.300 0.325 e eb - 0.430 l 0.115 0.150 0 15 0.100 bsc p1 18 (300 mil) plastic dual in-line package
p4c148/p4c149 page 10 of 10 document # sram104 rev c revisions document number : sram104 document title : p4c148/p4c149 ultra high speed 1k x 4 static cmos rams rev. issue date orig. of change description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid b apr-07 jdb added 45 and 55 ns speeds c nov-07 jdb removed reference to p4c148 military from cover page
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